The present invention relates to a JPEG image processing circuit for encoding/decoding the JPEG format (JPEG Encoding/Decoding), which is a standard format for still images and, more particularly, to a JPEG image processing circuit having a plurality of JPEG processing cores and performing processes in parallel.
A digital camera is a typical example of a system that handles the JPEG format (a JPEG image processing circuit). A digital camera is explained below as an example, however, the present invention is not limited to this, but can be applied to any JPEG image processing circuit that handles the JPEG format. In a digital camera, besides the JPEG conversion processes, actual image data is captured and the data is stored in a common memory or a storage device. Further, moving images or still images are displayed on a display unit of a system (in general, an LCD device), data is output to an external output terminal, or reversely, data is input from an external input terminal.
As these images are input/output in formats conforming various standards, the process of handling these images must be done in real time. Because of this, the JPEG encoding/decoding process, which is performed independently of the process which must be done in real time, is not strictly required to be done in real time although the performance itself is one of the factors of the system. Therefore, in many cases, a product to be put on a market where priority is given to low-cost, such as a consumer market, employs a configuration in which a common memory or a storage device for storing data and a plurality of functional modules are connected by a single common bus and the common bus is assigned to the plurality of functional modules in a timeshared manner and the functional module to which the common bus has been assigned accesses the common memory and the storage device.
Patent document 1: Japanese Unexamined Patent Publication (Kokai) No. 10-304356
Patent document 2: Japanese Unexamined Patent Publication (Kokai) No. 2001-005552